A complete account of every project, grant, and design-stage investment under ISM 1.0.
And a brief look at why the next phase, focused on the equipment, materials, and IP that fabs consume, may turn out to be the harder problem.
In the summer of 2023, the cleverer sort of person in Delhi had a settled view of the India Semiconductor Mission.
It was, depending on the dinner party, either a vanity project, a subsidy giveaway, or a Vedanta press release with a government letterhead. When Foxconn walked away from its $19.5bn joint venture with Anil Agarwal's mining group that July, the obituaries practically wrote themselves. India, the chorus went, would never make a chip.
Three years on, the mood is rather different. On May 5th 2026 the Union cabinet approved Crystal Matrix and Suchi Semicon, two semiconductor units in Gujarat worth a combined Rs 3,936 crore. They were, by Ashwini Vaishnaw's own admission, the last to be cleared under the first phase of the mission.
With them, the tally stands at twelve sanctioned units across seven states, with cumulative committed investment of roughly Rs 1.64 lakh crore - close to $19bn, or, as it happens, almost exactly the sum Foxconn was supposed to provide on its own. India does not yet make a leading-edge logic chip. But it has now shipped its first DRAM module to Dell, opened its first multi-chip-module line, broken ground on a glass-substrate packaging plant, and signed a technology-transfer pact with Taiwan for a 28-nanometre fab. The cynics, for once, were too clever by half.
How did this happen?
The answer lies partly in the architecture of the mission, partly in the discipline of its course-corrections, and partly in the decision - radical for an Indian industrial policy - to pay people to do what was actually possible rather than what looked best in a press release.
FOUR SCHEMES, ONE PURPOSE
The cabinet cleared the original Programme for Development of a Semiconductor and Display Manufacturing Ecosystem in December 2021, with a headline outlay of Rs 76,000 crore. The mission itself was operationalised the following year as an autonomous business division within MeitY, modelled loosely on Singapore's Economic Development Board. It rests on four pillars:
- The Semiconductor Fab Scheme. Up to 50% of project cost on a pari-passu basis for makers of logic, memory or analog chips.
- The Display Fab Scheme. The same 50% support for TFT-LCD and AMOLED panel manufacturers.
- The Compound Semiconductors, Silicon Photonics, Sensors, Discrete Devices and ATMP/OSAT Scheme. Covers everything from gallium-nitride power devices to the assembly-and-test plants that turn raw silicon into packaged chips. Originally pegged at 30%, the support was raised to 50% in September 2022 - a revision that proved decisive, opening the door to nine of the twelve eventual approvals.
- The Design Linked Incentive Scheme. Run by the Centre for Development of Advanced Computing, it reimburses up to half of design expenditure for fabless startups, capped at Rs 15 crore per firm, with a deployment incentive of up to 6% of net sales.
The early returns were dreadful. Vedanta-Foxconn collapsed in July 2023 over thin technology partnerships and Mr Agarwal's leverage; the consortium led by Israel's Tower Semiconductor with the Abu Dhabi-based Next Orbit Ventures, and Singapore's International Semiconductor Consortium, both lapsed.
Then, in June 2023, Micron Technology became the first sanction, and the programme's centre of gravity quietly shifted from chasing leading-edge fabs to building out the unsexy middle of the value chain.
THE TRAILBLAZER
Micron's plant at Sanand in Gujarat was the proof of concept. With a total outlay of around Rs 22,500 crore, the Centre underwriting half and Gujarat a further fifth, the American memory-maker's own cash commitment came to about $825m.
The facility - one of the world's largest single-raised-floor cleanrooms, at roughly 500,000 sq ft - was inaugurated by Narendra Modi on February 28th 2026. Within weeks it was shipping packaged DRAM modules to Dell's Indian laptop assembly lines: the first commercially sold "Made in India" semiconductor product. Mr Vaishnaw believes Sanand will eventually handle nearly a tenth of Micron's global memory output. Some 5,000 direct and 15,000 indirect jobs are projected.
What followed, on February 29th 2024, was the moment the mission stopped being aspirational. In a single cabinet sitting, three projects worth Rs 1.26 lakh crore were cleared - the trio that finally made the programme credible:
Tata Electronics' fab at Dholera, Gujarat (Rs 91,000 crore). A joint venture with Taiwan's Powerchip Semiconductor Manufacturing Corporation, the plant will produce 50,000 12-inch wafers a month at nodes between 28nm and 110nm: not the bleeding edge, but precisely the workhorse processes used in power-management ICs, microcontrollers, automotive logic and display drivers, where demand is durable and margins survive. A definitive technology-transfer agreement with Powerchip was signed in September 2024; tooling deals with Tokyo Electron followed; the special economic zone was notified in April 2026. First commercial silicon is targeted for December 2026.
Tata's assembly-and-test facility at Jagiroad, Assam (Rs 27,000 crore). Designed to package 48m chips a day for the automotive, mobile and AI markets. A partnership with Japan's ROHM was finalised in late 2025 for automotive-grade silicon MOSFETs; commercial shipments are expected in the first half of 2026.
CG Power's plant at Sanand (Rs 7,600 crore). A joint venture with Renesas of Japan and Stars Microelectronics of Thailand, targeting 15m units a day across various advanced packages. Its first line went live in August 2025, making it India's first end-to-end assembly-and-test facility.
How phase one unfolded: Foxconn's exit in July 2023, the Tata trio cleared in February 2024, and the closing approvals in May 2026.BEYOND GUJARAT
By the autumn of 2024 the mission had outgrown its initial geography. Two more approvals broke fresh ground:
Kaynes Semicon at Sanand (Rs 3,300 crore, September 2024). The smallest of the early projects but the second to ship: Mr Modi inaugurated it on March 31st 2026, and it became India's first plant to deliver multi-chip modules to commercial customers in the industrial, automotive, electric-vehicle and consumer-electronics segments.
HCL-Foxconn at Jewar, Uttar Pradesh (Rs 3,706 crore, May 2025). The first project outside Gujarat-Assam, and a quiet reconciliation with the partner that had walked away two years earlier. The plant will package 36m display-driver-IC units a month, plugging India's most painful import dependency in consumer electronics.
In a single announcement on August 12th 2025, four further projects were sanctioned, fanning the mission across three new states:
SiCSem, Bhubaneswar, Odisha (Rs 2,067 crore). A partnership with Britain's Clas-SiC Wafer Fab to build India's first commercial silicon-carbide compound-semiconductor fab, targeting electric vehicles, fast chargers, missiles and solar inverters.
3D Glass Solutions, Bhubaneswar (Rs 1,943 crore). The American firm will set up the country's first glass-substrate packaging unit. Groundbreaking happened in April 2026; commercial production is targeted for August 2028.
Continental Device India, Mohali, Punjab. A brownfield expansion of an existing discrete-semiconductor plant to 158m MOSFETs, IGBTs and Schottky diodes a year.
ASIP Technologies, Andhra Pradesh (Rs 468 crore). A system-in-package facility, with South Korea's APACT.
The closing pair, approved this month, fit the same pattern of careful niche-filling:
Crystal Matrix, Dholera (Rs 3,068 crore). An integrated GaN compound-semi fab and assembly unit for Mini and Micro-LED displays - televisions, automotive screens and extended-reality headsets.
Suchi Semicon, Surat (Rs 868 crore). Formalises a discrete-packaging line that had been operating in pilot mode since 2024.
All twelve units sanctioned under phase one of the India Semiconductor Mission, ranked by committed investment in crore rupees.THE UNSUNG HALF
Hardware headlines obscure the second half of the mission: a quieter design-and-talent build that may matter more in the long run. The Design Linked Incentive scheme has by early 2026 committed roughly Rs 234 crore to two dozen chip-design startups whose combined project costs come to nearly Rs 690 crore.
The beneficiaries form an emergent fabless cohort:
Where the money landed: Gujarat hosts seven of the twelve units and accounts for roughly four-fifths of committed investment.- Calligo Tech. RISC-V plus POSIT accelerators for high-performance computing.
- Mindgrove Technologies. An IIT-Madras spinout producing Shakti-RISC-V vision SoCs; has raised Rs 85 crore in private capital.
- Netrasemi. 12-nm edge-AI chips delivering 64 trillion operations per second for surveillance and robotics.
- Saankhya Labs. 5G telecom SoCs, in the Tejas Networks orbit.
- Fermionic Design. Satellite-communications chips.
- InCore Semiconductors. India's indigenous Dolomite RISC-V core.
Sixteen tape-outs, six fabricated ASICs and ten patents have already emerged from the cohort.
The talent pipeline is being built through the Chips-to-Startup programme, a Rs 250-crore scheme that aims to train 85,000 engineers. By early 2026 it had already trained over 67,000 students at 315 universities, with 122 academic tape-outs and 56 chips fabricated at the Semiconductor Laboratory in Mohali. C-DAC's ChipIN Centre in Bengaluru has signed access deals with Synopsys, Cadence, Siemens EDA and Keysight, and joined Arm's Flexible Access for Startups programme - putting tools that go down to 5nm within reach of 104 startups and over 250 academic institutions, which between them have logged more than 22m EDA tool-hours.
Add the Scheme for Promotion of Manufacturing of Electronic Components and Semiconductors (now superseded by a Rs 40,000-crore Electronics Components Manufacturing Scheme), the Rs 4,500-crore modernisation of the SCL Mohali fab approved in November 2025, and the announced India Semiconductor Research Centre - pitched as a domestic equivalent of Belgium's IMEC - and what looked four years ago like a single subsidy line begins to resemble a vertically integrated industrial strategy.
The design and talent build-out alongside the fab approvals: 24 fabless startups funded, 67,000 engineers trained, and 56 chips fabricated at SCL Mohali by early 2026.WHAT IT ADDS UP TO
The mission will not, by itself, give India sovereign chip-making at the leading edge. The Tata-Powerchip fab, when it opens in late 2026, will be a 28-nanometre-and-up plant: useful, profitable, but a generation behind TSMC. The dozen approved units skew heavily towards packaging, where the technology bar is lower and the geopolitical premium higher.
That, however, was the point. The bet - and on the evidence of 2024-26, a shrewd one - was that packaging is the rebalancing layer of the global semiconductor map. With chiplets, advanced 3D heterogeneous integration and silicon-carbide power devices accounting for ever more of a chip's value, an assembly-led entry was the path of least resistance.
Two of the twelve plants are already shipping commercially; two more are in qualification; the remaining seven are at various stages of construction. Crucially, no major foreign semiconductor firm has cancelled an Indian project since Foxconn's 2023 retreat.
The political economy has been quietly remarkable too.
Each approval has been twinned with state-level subsidies - Gujarat's standard 20%, Odisha's matching grants, Uttar Pradesh's land deal at Jewar - forcing chief ministers to compete in a way that mirrors the contest among American governors over CHIPS Act money.
Seven states now host a project, and yet the agglomeration logic of Sanand and Dholera has been preserved.
The next phase will be harder. ISM 2.0, launched in the February 2026 budget with a seed allocation of Rs 1,000 crore for the coming financial year, pivots from fabs to what they consume: semiconductor-manufacturing equipment, ultra-pure specialty gases and chemicals, photoresists and photomasks, silicon-wafer making, advanced design IP, and the long-deferred R&D centres.
Vaishnaw talks of a 20-year roadmap to 3-nanometre and 2-nanometre capabilities, and of meeting 70-75% of domestic chip demand by 2029.
That is the right next problem to have. The world's most expensive choke-points in chip-making are no longer the fabs but the EUV lithography tool, the photoresists that cost more per gramme than gold, and the rare gases produced by a handful of plants in Ukraine and Texas. India is unlikely to dethrone ASML this decade.
But by the time the Tata-Powerchip fab in Dholera ships its first commercial wafer in December, the country will have done something that looked impossible in mid-2023: it will have a real, multi-state, multi-company, partly-shipping semiconductor industry. Phase one is over. The harder, less photogenic phase two has begun.